Field of the Invention
The present invention relates to a switch circuit provided at a terminal at which a positive or negative voltage is inputted to an internal circuit of a semiconductor device.
Background Art
FIG. 4 is a circuit diagram showing a related art switch circuit. The switch circuit controls whether to transmit a positive or negative voltage inputted to an input terminal IN to an internal circuit 15 or shut off the positive or negative voltage, according to a signal of a switch control terminal EN.
Consider where the positive voltage VIN+ inputted from the input terminal IN is caused to be transmitted to a node B which is an input terminal of the internal circuit 15. The signal of the switch control terminal EN is made to be a VDD voltage in an active state to turn ON NMOS transistors 11 and 12. Here, the VDD voltage is a power supply voltage of the internal circuit 15. Further, a level shifter circuit 18 is configured to convert the signal of the input terminal LI into a voltage by the voltage of a power supply terminal LV and output the voltage from an output terminal LO and thereby to reverse the logic of the input and output. When the signal of the input terminal LI is of the VDD voltage, the level shifter circuit 18 outputs a signal of a GND voltage from the output terminal LO.
When the signal of the input terminal LI is of the GND voltage, the level shifter circuit 18 outputs a signal of the voltage of the power supply terminal LV from the output terminal LO. Thus, the level shifter circuit 18 outputs the GND voltage. When the voltage VIN+ is a voltage less than or equal to (|VGSP1|+|VOVP1|), the level shifter circuit 18 turns OFF a PMOS transistor 16. When the voltage VIN+ is a voltage greater than or equal to (|VGSP1|+|VOVP1|), the level shifter circuit 18 turns ON the PMOS transistor 16. Here, VGSP1 is a threshold voltage (VGSP1<0V) of each of the PMOS transistors 16 and a PMOS transistor 17. VOVP1 is an overdrive voltage (VOVP1<0V) necessary to reliably turn ON the PMOS transistors 16 and 17. Further, since the signal of the switch control terminal EN becomes the GND voltage through an inverter 14, the PMOS transistor 17 is turned ON. Thus, the positive voltage VIN+ inputted from the input terminal IN is transmitted to the node B which is the input terminal of the internal circuit 15. At this time, since an NMOS transistor 13 is being turned OFF, it does not affect the voltage of the node B.
Further, since the voltage at which the voltage VIN+ is greater than or equal to the GND voltage and less than or equal to (|VGSP1|+|VOVP1|) can be transmitted to the node B through the NMOS transistors 11 and 12, the voltage at which the voltage VIN+ is greater than or equal to (|VGSP1|+|VOVP1|) and less than or equal to (VDD-VGSN1-VOVN1) can be transmitted to the node B through either the NMOS transistors 11 and 12 or the PMOS transistors 16 and 17, and the voltage at which the voltage VIN+ is greater than or equal to (VDD-VGSN1-VOVN1) and less than or equal to VDD can be transmitted to the node B through the PMOS transistors 16 and 17, the positive voltage VIN+ inputted from the input terminal IN can be transmitted to the node B between the GND voltage at minimum and the VDD voltage at maximum.
Here, VDD is a power supply voltage, VGSN1 is a threshold voltage (VGSN1>0V) of each of the NMOS transistors 11 and 12, and VOVN1 is an overdrive voltage (VOVN>0V) necessary to reliably turn ON the NMOS transistors 11 and 12.
Next, consider where the positive voltage VIN+ inputted from the input terminal IN is not caused to be transmitted to the node B taken as the input of the internal circuit 15. The signal of the switch control terminal EN is made to be a GND voltage in an inactive state. Since the GND voltage is inputted to the input terminal LI, the level shifter circuit 18 outputs the same voltage as VIN+ connected to the power supply terminal LV from the output terminal LO. Since a gate of the NMOS transistor 13 is at the VDD voltage and a source thereof is at the GND voltage, the NMOS transistor 13 is turned ON to bring a node A to the GND voltage. Since a gate and a source (node A) of the NMOS transistor 11 are at the GND voltage, the NMOS transistor 11 is turned OFF. Since a gate and a drain (node A) of the NMOS transistor 12 are at the GND voltage, the NMOS transistor 12 is turned OFF. Since a gate and a source (input terminal IN) of the PMOS transistor 16 are at the voltage VIN+, the PMOS transistor 16 is turned OFF. Since a gate of the PMOS transistor 17 is at the VDD voltage and a drain (node B) thereof is less than or equal to the VDD voltage, the PMOS transistor 17 is turned OFF. Thus, the positive voltage VIN+ inputted from the input terminal IN is not transmitted to the node B taken as the input of the internal circuit 15.
Next, consider where the negative voltage VIN− inputted from the input terminal IN is not caused to be transmitted to the node B taken as the input of the internal circuit 15. The signal of the switch control terminal EN is made to be the GND voltage in the inactive state. Since, however, the negative voltage VIN− lower than the GND voltage is applied to the input terminal IN, the NMOS transistor 11 is brought into an ON state in a weak inversion region. Here, since the NMOS transistor 13 is turned ON, the node A is not brought to the input negative voltage VIN−, but to the GND voltage. Since the gate and source of the NMOS transistor 12 are at the GND voltage, the NMOS transistor 12 is turned OFF. Since VIN− is applied to the gate, source and backgate of the PMOS transistor 16, the PMOS transistor 16 is turned OFF. Since the gate of the PMOS transistor 17 is at the VDD voltage and the node B is at less than or equal to the VDD voltage, the PMOS transistor 17 is turned OFF. Thus, the negative voltage VIN− inputted from the input terminal IN is not transmitted to the node B taken as the input of the internal circuit 15.
Thus, the related art switch circuit is capable of preventing the negative voltage from being transmitted to the input of the internal circuit 15 even if the negative voltage is inputted from the input terminal IN, and preventing the malfunction of the internal circuit.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2013-183206